Advances in the semiconductor field have enabled multiple processor cores to be included within a single microchip. Each processor core may include an input/output (I/O) pin testing interface for testing and debugging. The incorporation of duplicate processor cores increases the number of I/O pins to be tested, as well as the time required to test the I/O pins. A serial approach of testing each processor core would multiply the test time according to the number of cores. Similarly, providing a test input and a test output for each processor core multiplies the number of required I/O pins. Therefore, the issue arises of how to efficiently test integrated circuits having a plurality of processor cores.